1. Field of the Invention
This invention relates to a dynamic memory device and a method for manufacturing the same, and more particularly to a dynamic memory device having a plurality of dynamic memory cells which are each constituted by one transistor and one capacitor and which are displaced from one another by 1/2.sup.n (n is a natural number equal to or larger than 2) in a channel length direction and a method for manufacturing the same.
2. Description of the Related Art
A dynamic memory device having a plurality of dynamic memory cells which are each constituted by one transistor and one capacitor and which are displaced from one another by 1/2.sup.n (n is a natural number equal to or larger than 2) in a channel length direction is disclosed in Published Unexamined Japanese Patent Application No. 61-274357, for example. The dynamic memory device disclosed in this specification is explained with reference to FIGS. 6A to 6D. In this case, FIG. 6A is a plan view showing the state in which cell plate electrodes are formed, FIG. 6B is a plan view showing the state in which transfer gates are formed, FIG. 6C is a plan view showing the state in which bit lines connected to the source/drain regions of transistors are formed, and FIG. 6D is a plan view showing the state in which word lines are formed.
In FIG. 6A, a field insulation film (not shown) is formed on the surface of a p-type semiconductor substrate, for example, to form element isolation regions. Element region 1 in which two memory cells are formed is formed in each element isolation region. Each element region 1 includes two capacitor forming regions 1.sub.1, two transistor forming regions 1.sub.2 and contact hole forming region 1.sub.3 for connection with a bit line. Element regions 1 which are adjacent in a channel width direction (in a direction indicated by arrow A in FIG. 6A) are displaced from each other by 1/4 pitch in a channel length direction (in a direction indicated by arrow B in FIG. 6A). Further, cell plate electrodes 2 are formed over element regions 1 through a capacitor insulation film. Each of cell plate electrodes 2 is arranged to extend in a oblique direction and cover the facing end portions of corresponding adjacent element regions 1. Groove portions 3 which are formed in a stepped configuration in positions corresponding to transistor formation regions 1.sub.2 of element region 1 are arranged between adjacent cell plate electrodes 2. In each capacitor forming region 1.sub.1 of each element region 1, an n-type diffusion layer is formed in the p-type substrate, and the n-type diffusion layer, capacitor insulation film, and cell plate electrode 2 are combined to form a capacitor.
Next, as is shown in FIG. 6B, transfer gate electrodes 4 are formed on an insulation film (not shown) by a mask-alignment process. Transfer gate electrodes 4 are formed over contact hole forming regions 4.sub.1 for connection with the word lines and gate electrode regions 1.sub.4 which are formed over element regions 1. 1
After this, as is shown in FIG. 6C, contact holes 5 are formed in an insulation film (not shown) in positions corresponding to respective contact hole forming regions 1.sub.3 of element regions 1 by a mask-alignment process. Then, bit lines 6 are formed in stripe configuration by the mask-alignment process so as to extend in the channel width direction. Bit lines 6 are connected to respective element regions 1 via contact holes 5.
Next, as is shown in FIG. 6D, contact holes 7 are formed in an insulation film (not shown) in positions corresponding to respective contact hole forming regions 4.sub.1 of transfer gate electrodes 4 by the mask-alignment process. Then, word lines 8 are formed in the stripe configuration to extend in the channel length direction by the mask-alignment process. Word lines 8 and transfer gate electrodes 4 are connected to each other via respective contact holes 7.
With the dynamic memory device of the above construction, the minimum width of cell plate electrode 2 of the capacitor can be made large in comparison with the conventionally well-known dynamic memory in which adjacent memory cells are displaced from each other by 1/2 pitch in the channel length direction, and therefore cell plate electrode 2 can be easily formed even when the cell size is reduced. For this reason, in order to enhance the integration density, it is advantageous to displace memory cells from each other by 1/4 pitch in the channel length direction.
However, as is shown in FIG. 6B, the shape of transfer electrode 4 formed over cell plate electrode 2 is complicated and is isolated in the island configuration. Therefore, it is necessary to form a fine gate electrode pattern. Thus, formation of transfer gate electrode 4 becomes difficult though the minimum width of cell plate electrode 2 can be made large and the cell plate electrode can be easily formed. As a result, much improvement of the integration density cannot be expected. Further, formation of contact hole 7 for connecting transfer gate electrode 4 with word line 8 necessitates the alignment tolerance for transfer gate electrode 4, lowering the integration density.